FIG. 1 illustrates the actual structure of a Plasma Display Panel, called hereinafter PDP. Video is sent to a digital board 10 including a PDP controller. This controller is an integrated circuit (IC) that takes care of all PDP relevant signal processing and converts video information into sub-field information. This controller is responsible for sending all power signals to data drivers 11, line drivers 12 and a common part 13 of the PDP. Line drivers 12 are responsible for selecting, one by one, the lines of cells to be written. Data drivers 11 are responsible for sending bits (0 or 1) on the vertical electrodes of all cells of the current selected lines. Finally, the common part 13 is responsible for generating global signals in combination with line drivers 12 like sustain signals, erase signals, priming signals . . . A PDP cell is present at the crossing point between a vertical electrode coming from a data driver output, a horizontal electrode coming from a line driver output and a horizontal electrode coming from the common part.
As illustrated by FIG. 2, each data driver 11 works as a serial to parallel converter. For a data driver with n outputs, the n data samples Cn,t for a line t are sent serially from the PDP controller 10 to said data driver. The input works at a frequency defined by a clock circuit. On each starting edge of an enable signal ENA, the n outputs of the data driver take the n last input values. In fact when the data Cn,t are sent to the input of the data driver, the outputs take the values Cn,t−1. The enable signal is included in the addressing signal used to activate the current line t−1. The important point is that the input signals are control logic signals (low voltage) whereas the output signals are power signal (high voltage≈60V). The global activity of the data driver is defined by two main parameters:                the number of changes occurring at the input of the driver during the loading of the data driver, and        the number of changes occurring at the output of the driver from one line to another.        
It is also important to notice how these changes are appearing. Indeed if all outputs have the same value and are changing in one time, this is less energy consuming than if each output is different and is changing.
Then, based on all these assumptions, a critical test pattern called hereinafter chequered pattern can be defined per driver as illustrated by FIG. 3. This chequered pattern, which is a bit series always toggling between 0 and 1, introduces an overheating of the data driver and above all when the addressing speed is fast (clk and ENA are high) like for high-resolution displays. If the data driver is overheated a long time (many frames) it can be definitely damaged. Moreover, today, the data drivers are bonded on the PDP glass by using glue and it is almost impossible to remove them in order to perform an exchange. Therefore, if a data driver has been damaged, the whole panel can be thrown away.
Today, there are mainly three possibilities to avoid such a problem:                limiting either the addressing speed, or the number of sub-fields used per frame;        using a specific coding that should reduce the situation depicted in FIG. 3 for standard picture (reducing the toggling inside a codeword),        detecting the critical patterns and reducing the number of sub-fields used during their addressing.        
Solutions consisting in detecting chequered patterns in video pictures to be displayed also exist but the problem is not solved because chequered patterns can also be introduced by the dithering operation applied to any pictures. Indeed in case of cell-based dithering as defined in WO 01/71702 and EP 1 262 947, the structure of dithering with a level ½ is exactly the chequered pattern. Such a dithering is illustrated by the following example. In this example, the sub-fields have the following weights: 1-2-3-5-8-13-18-26-39-57-83. The following pixel values can be displayed:                0: 00000000000        ( . . . )        46: 01011110000        56: 10111101000        ( . . . )        255: 11111111111        
The dithering consists in associating to each pixel value V of the picture to be displayed a dithering level L used to dither between two different pixel values V1 and V2 that can be coded by the given set of subfields such that V=(1−L)×V1+L×V2 with V1<V2 and Lε[0, 1]. The pixel values can be displayed by a group of adjacent cells (or luminous elements) of the panel or by a same cell on a plurality of frames. In the present case, to render the pixel value V=51, we will use spatial dithering of level ½ with the pixel values V1=46 and V2=56 So if a uniform gray level with value 51 is to be displayed on the whole panel, the following picture pixel values are displayed during one frame:
4656465646564656465646564656465646564656564656465646564656465646564656465646564646564656465646564656465646564656465646565646564656465646564656465646564656465646465646564656465646564656465646564656465656465646564656465646564656465646564656464656465646564656465646564656465646564656564656465646564656465646564656465646564646564656465646564656465646564656465646565646564656465646564656465646564656465646
The subfield information sent to the data drivers are given by the following tables.
1st sub-field01010101010101010101101010101010101010100101010101010101010110101010101010101010010101010101010101011010101010101010101001010101010101010101101010101010101010100101010101010101010110101010101010101010
2nd sub-field10101010101010101010010101010101010101011010101010101010101001010101010101010101101010101010101010100101010101010101010110101010101010101010010101010101010101011010101010101010101001010101010101010101
3rd sub-field01010101010101010101101010101010101010100101010101010101010110101010101010101010010101010101010101011010101010101010101001010101010101010101101010101010101010100101010101010101010110101010101010101010
4th, 5th and 6th sub-fields11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
7th sub-field10101010101010101010010101010101010101011010101010101010101001010101010101010101101010101010101010100101010101010101010110101010101010101010010101010101010101011010101010101010101001010101010101010101
8th sub-field01010101010101010101101010101010101010100101010101010101010110101010101010101010010101010101010101011010101010101010101001010101010101010101101010101010101010100101010101010101010110101010101010101010
9th, 10th and 11th sub-fields00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
As it can be seen in the previous tables, 5 sub-fields will use a chequered pattern. This means that even with a standard picture, the data driver overheat problem may occur because of dithering.